The present invention relates to a method and/or architecture for latches generally and, more particularly, to a method and/or architecture for a silicon, oxide, nitride, oxide, silicon (SONOS) technology latch.
Conventional static random access memories (SRAMs) can include a combination of volatile circuits such as latch circuits coupled to nonvolatile (NV) circuits such as EPROM and EEPROM. Data can be programmed into the NV circuits and loaded into the latch circuits at startup.
Conventional latch and NV storage designs have the following disadvantages: (i) data can be transferred from the non-volatile memory to the latches only at startup, (ii) lack of non-volatile memory re-programmability (i.e., some conventional NV storage is only one-time programmable unless a UV window is provided), (iii) a separate sequencer (i.e., in PLD applications) and/or latches are required to transfer data from the NV storage to the latch or a RAM array, and/or (iv) lack of capability to read from or write to the latches dynamically (i.e., latches are not dynamically programmable).
It would be desirable to have a method and/or architecture for a latch that may (i) read from or write to the latch from a data bus, (ii) transfer data from non-volatile (NV) storage to the latch (e.g., initialize the latch with NV data), and/or program the NV storage with latch data.
The present invention concerns an apparatus comprising a latch circuit, a non-volatile storage circuit, and a switching circuit. The latch circuit may be configured to be dynamically programmable. The non-volatile storage circuit may be configured to be re-programmable. The switching circuit may be configured to transfer data from (i) the non-volatile memory element into the latch circuit in response to a first control signal, and (ii) the latch circuit into the non-volatile memory circuit in response to a second control signal.
The objects, features and advantages of the present invention include providing a method and/or architecture for a silicon, oxide, nitride, oxide, silicon (SONOS) latch that may (i) read from or write to a data bus, (ii) receive data from a non-volatile (NV) storage element, (iii) be initialized with data stored in the NV storage element, (iv) re-program the NV storage element with latch data, (v) dynamically program the NV storage element, and/or (vi) be implemented as a three-section (e.g., a read/write latch, a switching circuit, and a non-volatile storage element) non-volatile SRAM cell.